bat365官网登录入口长聘教授、博士生导师，教育部长江学者特聘教授，国家级一流本科课程负责人。

1999年和2004年分别在清华电子工程系和微电子所获得学士和博士学位。2004年留在清华微电子所任教，2006年~2017年分别在欧洲微电子中心、麻省理工学院、林肯大学、牛津大学进修与访问。长期从事软件定义芯片、硬件安全和密码芯片、VLSI数字信号处理等研究工作。发表高水平论文300余篇、授权发明专利150余项（美国专利20余项）、撰写著作9部、参与制定国家标准1项。担任国际权威期刊《IEEE Circuits and Systems Magazine》副主编、中国工程院院刊《信息与电子工程前沿》执行副主编；密码硬件顶级会议CHES、集成电路设计顶级会议ISSCC，及电子设计自动化顶级会议DAC的TPC委员，集成电路设计一流会议A-SSCC的TPC委员和大会主席等；中国密码学会密码芯片专委会副主任委员；ISO/IECJTC1/SC27 国际标准注册专家。关键技术在一系列国家重大工程中取得批量应用。获国家技术发明二等奖、中国专利金奖、教育部技术发明一等奖、中国电子学会技术发明一等奖、世界互联网大会15项世界互联网领先科技成果等奖励。

主持3门课，获首批国家级一流本科课程、清华大学本科生精品课、北京市青年教师教学竞赛一等奖、清华大学青年教师教学竞赛一等奖、清华大学青年教师教学优胜奖、MOOC教学先锋奖等多个教学奖励，所负责的大规模网络开放课程（MOOC）入选首批教育部高校在线教学国际平台，并获得清华大学“良师益友”称号。

[PROFESSIONAL CAREER]

[EDUCATION]

[CURRENT RESEARCH]

[TEACHING]

1. Foundation of Integrated Circuits I, course number: 30260163, Mandatory Course for Undergraduates, Every Fall Semester since 2018.

2. Digital Integrated Circuit: Analysis & Design, course number: 40260173, Mandatory Course for Undergraduates, Every Fall Semester during 2005-2018.

3. VLSI Digital Signal Processing: course number 81020082, Elective Course for Graduate Students, Every Spring Semester during 2006-2012, and 2017 to date.

4. Digital Integrated Circuit: Analysis & Design, Massive Open Online Course (MOOC), Every Semester since 2015, Link: http://www.xuetangx.com/courses/course-v1:TsinghuaX+40260173_X+sp/about

[AWARDS AND HONORS]

RESEARCH

1. National Award for Technological Invention; The Second Prize; Winners: Shaojun Wei, Leibo Liu, Zhigang Mao, Longxing Shi, Shouyi Yin and Yuliang Deng; 2015 (Note: this is one of the three most prestigious national-level awards in science and technology awarded by the government of P. R. China).

2. Technological Invention Award by the Chinese Institute of Electronics; The First Prize; Winners: Leibo Liu, Min Zhu, Jianfeng Zhu, Chenchen Deng, Shaojun Wei and Shouyi Yin; 2021.

3. Chinese Patent Golden Award, by the World Intellectual Property Organization (WIPO) and the State Intellectual Property Office of China (SIPO); Winners: Leibo Liu, Min Zhu, Yansheng Wang, Jianfeng Zhu, Jun Yang, Peng Cao, Longxing Shi, Shouyi Yin and Shaojun Wei; 2015 (Note: this is the highest government award for Intellectual Property in P. R. China).

4. Technological Invention Award by the Ministry of Education; The First Prize; Winners: Shaojun Wei, Longxing Shi, Leibo Liu, Shouyi Yin, Jun Yang and Weifeng He; 2014.

5. Technological Invention Award by the Chinese Institute of Electronics; The First Prize; Winners: Shouyi Yin, Shaojun Wei, Peng Ouyang, Xiudong Li, Leibo Liu, Shibin Tang; 2020.

6. World Leading Internet Scientific and Technological Achievement: the 5^th World Internet Conference(WIC 2018)

7. Best Paper Nomination: Design Automation Conference 2017, 2019(DAC’ 2017, DAC’ 2019)

8. Design Contest Award: the 23^rd International Symposium on Low Power Electronics and Design 2017 (ISLPED 2017).

9. Science and Technology Progress Award by Jiangxi Province; The Second Prize; Winners: Shouyi Yin, Li Lin, Renjun Cheng, Leibo Liu, Bo Lan, Zhiming Zhang, Huiqin Wan and Yan Xu; 2014.

TEACHING

1. First Batch of National First-class Undergraduate Course, by the Ministry of Education of the People's Republic of China, 2020.

2. "Good Mentor and Friend" award of Tsinghua University, 2023.

3. A First Prize Winner in the Teaching Competition for Young Faculties in Universities in Beijing, by the Government of Beijing, 2011 (Note: One of the 18 winners among 400 candidates from more than 50 Universities in Beijing).

4. Outstanding Teaching Award for Young Faculties in Tsinghua University, 2011 (Less than 10 young faculties are awarded each year in Tsinghua University).

5. Outstanding Undergraduate Course Award in Tsinghua University, 2010 (Less than 10 out of 100 undergraduate courses in Tsinghua University are identified as “top-quality undergraduate courses”).

6. A First Prize Winner in the Teaching Competition for Young Faculties in Tsinghua University, 2010.

7. Teaching Achievements Award in Tsinghua University, The Second Prize, Winners: Leibo Liu, Dong Wu, Xingjun Wu and Runde Zhou, 2012.

8. LIAO KAIYUAN Teaching Awards, Awarded by Tsinghua University Education Foundation, 2012.

[PUBLIC SERVICES]

IEEE Asian Solid-State Circuits Conference (IEEE A-SSCC)

Ø Conference Chair, 2023

Ø Technical Program Committee (TPC) Member, 2008 - Present

Ø Technical Program Committee (TPC) Vice Chair, 2013

Conference on Cryptographic Hardware and Embedded Systems (CHES)

Technical Program Committee (TPC) Member, 2023-2024

Design Automation Conference(DAC)

Ø Technical Program Committee (TPC) Member, 2016-2019

IEEE CAS Visual Signal Processing and Communication (VSPC)

Ø Technical Program Committee (TPC) Member, 2016-Present

IEEE/ACM International Symposium on Microarchitecture (MICRO)

Ø External Review Committee Member, 2017

《IEEE Circuits and Systems Magazine》

Ø Associate Editor-in-Chief

《Frontiers of Information Technology & Electronic Engineering》

Ø Executive Associate Editor-in-Chief

Cryptographic IC Technical Committee, Chinese Association for Cryptologic Research

Ø Deputy Director, 2018 - Present

[PUBLICATIONS]

BOOKS

Shaojun Wei, Leibo Liu, Jianfeng Zhu, Chenchen Deng, “Software Defined Chips”(Volume I), Springer Singapore, 2023. ISBN：978-981-19-6993-5. (In English, 390,000Words, 4 Chapters, 316Pages).

Leibo Liu, Shaojun Wei, Jianfeng Zhu, Chenchen Deng, “Software Defined Chips”(Volume II), Springer Singapore, 2023. ISBN：978-981-19-7635-3. (In English, 410,000Words, 5 Chapters, 330Pages).

Shaojun Wei, Leibo Liu, Jianfeng Zhu, Chenchen Deng, “Software Defined Chips”(Volume I), China Science Press, 2021. ISBN：978-7-03-068779-1. (In Chinese, 350,000Words, 4 Chapters, 278Pages).

Leibo Liu, Shaojun Wei, Jianfeng Zhu, Chenchen Deng, “Software Defined Chips”(Volume II), China Science Press, 2021. ISBN：978-7-03-068780-7. (In Chinese, 380,000Words, 5 Chapters, 301Pages).

Leibo Liu, Guiqiang Peng, Shaojun Wei, “Massive MIMO Detection Algorithm and VLSI Architecture”, Springer Singapore, 2019. eBook ISBN：978-9811363610. (In English, 450,000Words, 7 Chapters, 370 Pages).

Leibo Liu, Guiqiang Peng, Shaojun Wei, “Massive MIMO Detection Algorithm and VLSI Architecture--the application specific integrated circuit and dynamic reconfigurable chip design”, China Science Press, 2018. ISBN：978-7-03-060210-7. (In Chinese, 350,000Words, 7 Chapters, 312Pages).

Leibo Liu, Bo Wang, Shaojun Wei, “Reconfigurable Cryptographic Processor”, Springer Singapore, 2018. Hardcover ISBN：978-981-10-8898-8, eBook ISBN：978-981-10-8899-5. (In English, 500,000Words, 7 Chapters, 386 Pages).

Leibo Liu, Bo Wang, Shaojun Wei, “Reconfigurable Computing Processor for Cryptographic Algorithms”, China Science Press, September 2017. ISBN: 9787030542441 (In Chinese, 434,000Words, 7 Chapters, 337 Pages).

Shaojun Wei, Leibo Liu, Shouyi Yin, “Reconfigurable Computing”, China Science Press, July 2014, ISBN: 9787030416346 (In Chinese, 680,000Words, 14 Chapters, 550 Pages).

PAPERS PUBLISHED IN ISSCC, JSSC, ASSCC IN RECENT YEARS

Note: Supervised students are indicated with an underline “_”.

Corresponding authors are indicated with an asterisk “*”.

[1] Yihong Zhu, Wenping Zhu, Yi Ouyang, Junwen Sun, Min Zhu, Qi Zhao, Jinjiang Yang, Chen Chen, Qichao Tao, Guang Yang, Aoyang Zhang, Shaojun Wei, Leibo Liu*. “A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems,” 2024 IEEE Journal of Solid-State Circuits (ISSCC), San Francisco, CA, USA.

[2] Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu*. A 28nm 48KOPS 3.4μJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems，2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA.

[3] Huiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu*. "A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction",2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[4] Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu*. "RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems." IEEE Journal of Solid-State Circuits, 58(1) (2023): 124 - 140.

[5] Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu*. "Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters", IEEE Journal of Solid-State Circuits, 56(8) (2021): 2585-2601.

[6] Huiyu Mo, Wenping Zhu, Wenjing Hu, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu*. " A 12.1 TOPS/W Quantized Network Acceleration Processor with Effective-Weight-Based Convolution and Error-Compensation-Based Prediction ", IEEE Journal of Solid-State Circuits , 57(5) (2022): 1542-1557.

[7] Guiqiang Peng, Leibo Liu*, Sheng Zhou, Shouyi Yin, and Shaojun Wei. "A 2.92-Gb/s/W and 0.43-Gb/s/MG flexible and scalable CGRA-based baseband processor for massive MIMO detection." IEEE Journal of Solid-State Circuits, 55(2)(2020): 505-519.

[8] Guiqiang Peng, Leibo Liu*, Qiushi Wei, Yao Wang, Shouyi Yin, and Shaojun Wei.“A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128*8 Massive MIMO Systems”, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, Taiwan.

[9] Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin. "TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration", 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[10] Zhiheng Yue, Yang Wang, Huizheng Wang, Yabing Wang, Ruiqi Guo, Limei Tang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin. "CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction", 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[11] Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin. "MulTCIM: A 28nm 2.24μJ/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers", 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[12] Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei,Yin Shouyi. "A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing ", 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[13] Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin. "A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration"，2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[14] Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin. "A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes", 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[15] Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin. "A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization", 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.

[16] Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin. "ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. " IEEE Journal of Solid-State Circuits, 58(1) (2023): 243 - 255.

[17] Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Yin Shouyi. "An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention." IEEE Journal of Solid-State Circuits, 58(1) (2023): 227 - 242.

[18] Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin. " TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization." IEEE Journal of Solid-State Circuits, 58(3) (2023): 852 - 866.

[19] Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin."TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes." IEEE Journal of Solid-State Circuits, 58(6)(2023): 1798 - 1809.

[20] Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, Shouyi Yin. "Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. " IEEE Journal of Solid-State Circuits, 57(10) (2022): 3164 - 3178.

[21] Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin. "TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs." IEEE Journal of Solid-State Circuits, 56(10) (2021): 3021- 3038

[22] Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie and Shouyi Yin. "Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning." IEEE Journal of Solid-State Circuits, 56(2) (2021): 658-673

[23] Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei. "An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width." IEEE Journal of Solid-State Circuits, 54(4)(2019): 1120-1136.

[24] Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei. "A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications." IEEE Journal of Solid-State Circuits, 53(4)(2018):968-982.

[25] X. Man, J. Zhu, G. Song, S. Yin, S. Wei, L. Liu*, "CaSMap: Agile Mapper for Reconfigurable Spatial Architectures by Automatically Clustering Intermediate Representations and Scatering Mapping Process"，2022 ACM/IEEE 49th Annual International Symposium on Computer Architecture (ISCA), Online.

[26] Y. Wu, L. Wang, X. Wang, J. Han, J. Zhu, H. Jiang, S. Yin, S. Wei, L. Liu*, "Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems"，2022 International Symposium on High-Performance Computer Architecture (HPCA), Online.

[27] Su, S., Yang, B., Rožić, V., Yang, M., Zhu, M., Wei, S., & Liu, L*., “A Closer Look at the Chaotic Ring Oscillators based TRNG Design”. 2023 IACR Conference on Cryptographic Hardware and Embedded Systems(CHES), Prague, Czech Republic.

[28] Chen, X., Yang, B., Zhu, J., Liu, J., Yin, S., Yang, G., ... & Liu, L* “UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication”. 2024 IACR Conference on Cryptographic Hardware and Embedded Systems(CHES), Halifax, Canada.

[29] Liu, J., Zhao, C., Peng, S., Yang, B., Zhao, H., Han, X., ... & Liu, L*. “A Low-Latency High-Order Arithmetic to Boolean Masking Conversion”. 2024 IACR Conference on Cryptographic Hardware and Embedded Systems(CHES), Halifax, Canada.

[30] X. Chen, B. Yang, S. Yin, S. Wei, L. Liu*, "CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme "，2022 IACR Conference on Cryptographic Hardware and Embedded Systems(CHES), Online.

[31] C. Zhao, N. Zhang, H. Wang, B. Yang, W. Zhu, Z. Li, M. Zhu, S. Yin, S. Wei, L. Liu*, "A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium"，2022 IACR Conference on Cryptographic Hardware and Embedded Systems(CHES), Online.

[32] W. Sun, Z. Li, S. Yin, S. Wei, L. Liu*, "ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast", 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), Online.

[33] L. Chen, J. Zhu, Y. Deng, Z. Li, J. Chen, X. Jiang, S. Yin, S. Wei, L. Liu*, "An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures", IEEE Transactions on Parallel and Distributed Systems (TPDS), 32(12) (2021): 3066 - 3080, DOI: 10.1109/TPDS.2021.3084804

[34] Y. Zhu, M. Zhu, B. Yang, W. Zhu, C. Deng, C. Chen, S. Wei, L. Liu*. "LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR", IEEE Transactions on Circuits and Systems I: Regular Papers, 68(3) (2021):1146-1159.

[35] H. Jiang, F. J. H. Santiago, H. Mo, L. Liu*, J. Han, "Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications", Proceedings of the IEEE, 108(12) (2020): 2108-2135,DOI: 10.1109/JPROC.2020.3006451

[36] L. Liu, X. Man, J. Zhu, S. Yin, S. Wei, "Pattern-Based Dynamic Compilation System for CGRAs with Online Configuration Transformation", IEEE Transactions on Parallel and Distributed Systems(TPDS). v 31, n 12, p 2981 - 2994, DOI: 10.1109/TPDS.2020.3007492.

[37] N. Zhang, B. Yang, C. Chen, S. Yin, S. Wei, L. Liu*, "Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT", Conference on Cryptographic Hardware and Embedded Systems (CHES 2020), Online, 14-17, September, 2020.

[38] Y. Yang, Z. Li, Y. Deng, Z. Liu, S. Yin, S. Wei, L. Liu*, "GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent", In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020.

[39] D. Chen, Z. Li, T. Xiong, Z. Liu, J. Yang, S. Yin, S. Wei, L. Liu*, "CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture", 2020 IEEE/ACM International Symposium on Microarchitecture (MICRO-53), Online.

[40] H. Mo, L. Liu*, W. Hu, W. Zhu, Q. Li, A. Li, S. Yin, J. Chen, X. Jiang, S. Wei, "TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks", 2020 IEEE/ACM International Symposium on Microarchitecture (MICRO-53), Online.

[41] L. Liu, J. Zhu, Z. Li, Y. Lu, Y. Deng, J. Han, S. Yin, S. Wei, "A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges and Applications", ACM Computing Surveys, 2019. DOI:10.1145/3357375

[42] P. Wang, L. Liu*, S. Zhou, G. Peng, S. Yin, S. Wei. "Near-Optimal MIMO-SCMA Uplink Detection with Low-Complexity Expectation Propagation." IEEE Transactions on Wireless Communications, 2019. DOI: 10.1109/TWC. 2019.2950314 [In Press]

[43] L. Wang, *L. Liu, J. Han, X. Wang, S. Yin, S. Wei. "Achieving Flexible Global Reconfiguration in NoCs using Reconfigurable Rings". IEEE Transactions on Parallel and Distributed Systems, 31(3) (2020): 611-622. DOI: 10.1109/TPDS.2019. 2940190

[44] L. Liu, A. Luo, G. Li, J. Zhu, Y. Wang, G. Shan, J. Pan, S. Yin, S. Wei. “Jintide^®: A Hardware Security Enhanced Server CPU with Xeon^® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Computing Processor”. 31st Hot Chips: A Symposium on High Performance Chips( Hot Chips 2019), Stanford, Palo Alto, CA, USA, 18-20, August, 2019

[45] Z. Li, *L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei. "FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory". In The 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52), October 12-16, 2019, Columbus, OH, USA.

[46] H. Mo, *L. Liu, W. Zhu, Q. Li, H. Liu, W. Hu, Y. Wang, S. Wei. “A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6, [Best Paper Nomination]

[47] X. Man, *L. Liu, J. Zhu, S. Wei. “A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1- 6

[48] H. Liu, *L. Liu, W. Zhu, Q. Li, H. Mo, S. Wei. “L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network”. 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2-7, June 2019, 1-6

[49] H. Yan, Z. Li, *L. Liu, S. Yin, S. Wei. "Constructing Concurrent Data Structures on FPGA with Channels." In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 172-177. ACM, 2019

[50] B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, Z. Zhou, S. Wei, “Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 12, no. 2, pp. 309-322, Feb. 2017. DOI: 10.1109/TIFS.2016.2612638.

[51] C. Yang, *L. Liu, K. Luo, S. Yin, S. Wei, “CIACP: A Correlation- and Iteration-Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 1, pp. 29-43, January 2017. DOI: 10.1109/TPDS.2016.2554278.

[52] Z. Li, *L. Liu, Y. Deng, S. Yin, Y. Wang, S. Wei, “Aggressive Parallelization of Irregular Applications on Reconfigurable Hardware,” in the 44th International Symposium on Computer Architecture (ISCA), Toronto, Canada, June, 2017, pp. 575-586.DOI: 10.1145/3140659.3080228

[53] Y. Lu, *L. Liu, Y. Deng, J. Weng, Z. Li, C. Deng and S. Wei, “Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution,” in the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June, 2017, pp.71-71. DOI: 10.1145/3061639.3062284.

[54] Q. Wang, *L. Liu, W. Zhu, H. Mo, C. Deng, S. Wei, “A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment,” in the 54th Annual Design Automation Conference (DAC 2017), Austin, TX, USA, June 2017, pp.57-57.DOI: 10.1145/3061639.3062182 [Best Paper Nomination].

[55] B. Wang, *L. Liu, C. Deng, M. Zhu, S. Yin, S. Wei, “Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 11, no. 6, pp. 1151-1164, 2016. DOI: 10.1109/TIFS.2016.2518130.

[56] W. Zhu, *L. Liu, G. Jiang, S. Yin, S. Wei, “A 135 fps 1080p 87.5 mW Binary Descriptor Based Image Feature Extraction Accelerator,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 26, no. 8, pp. 1532-1543, 2016. DOI: 10.1109/TCSVT.2015.2469116.

[57] C. Yang, *L. Liu, S. Yin, and S. Wei, “Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays,” in the 53rd Annual Design Automation Conference (DAC 2016), Austin, TX, United States, June, 2016, pp. 1-6. DOI: 10.1145/2897937.2898001