Wei Deng Associate Professor

Email：wdeng@tsinghua.edu.cn

Phone: +86-10-62792712

Address: School of Integrated Circuits, Tsinghua University, Haidian District, Beijing 100084

Prof. Wei Deng is currently an Associate Professor with the School of Integrated Circuits at Tsinghua University, Beijing, China. He received the B.S. and M.S. degrees in electronic engineering from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. From 2013 to 2014, he was a Post-Doctoral Researcher with the Tokyo Institute of Technology. From 2015 to 2019, he was with Apple Inc., Cupertino, CA, USA, working on radio frequency (RF), millimeter-wave (mm-wave), and mixed-signal IC design for wireless transceivers and Apple A-series processors. Since 2019, he has been a Faculty Member with the School of Integrated Circuits, Tsinghua University, Beijing, China. He has authored or co-authored over 160 IEEE journal and conference articles including 30+ ISSCC and JSSC. He holds/filed 40+ patents. His research interests include RF; mm-wave; terahertz; and mixed-signal integrated circuits and system for wireless communications, sensing, and imaging systems. Dr. Deng currently serves as a Technical Program Committee Member for ISSCC, VLSI, CICC, A-SSCC, and ESSCIRC. He is a Guest Editor and an Associate Editor of the IEEE Solid-State Circuits Letters (SSC-L), a Guest Editor of the IEEE Journal of Solid-state Circuits (JSSC), and a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).  He has been PI of several research projects funded by MOST and leading global companies. He was a recipient of several national and international awards, including the IEEE SSCS Predoctoral Achievement Award, the Tejima Research Award, and the IEEE/ACM ASP-DAC Best Design Award.

Group Openings: Our group has openings for 4-5 PhD/Master students every year and regularly recruit postdocs with related background in RF, mm-wave, THz and mixed-signal integrated circuits and system design. Undergraduate students are also encouraged to participate in our research. For more information, please email /index.html with your CV.

Research Interests:

· Silicon-based RF/mixed-signal, millimeter-wave, and THz integrated circuits and systems

Major Publications

[1] B. Zhu, W. Deng, Z. Huang, H. Jia, H. Jia, A. Yan, Y. Yang, J. Liu, Y. Fu, S. Sun, C. Tang, L. Kuang, L. Yu, Y. Liu, X. Liang, Z. Wang, and B. Chi, “A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z- Compliant Joint-Radar-Communication-Location Transceiver SoC,” in IEEE Journal of Solid-State Circuits (JSSC), 2025

[2] P. Guan, R. Ma, H. Jia, W. Deng, M. Deng, J. Xue, A. Yan, S. Sun, Q. Peng, T. Siriburanon, R. Staszewski, Z. Wang, and B. Chi, "A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3432759. Oct. 2024（Invited paper）

[3] S. Zhang, W. Deng, H. Jia, H. Liu, S. Sun, P. Guan, Z. Wang, and B Chi "A Transformer-Based Series-Resonance CMOS VCO," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3433521.

[4] X. Huang, H. Jia, W. Deng, Z. Wang and B. Chi, "A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS," in IEEE Journal of Solid-State Circuits (JSSC), Oct. 2024 doi: 10.1109/JSSC.2024.3404610. （Invited paper）

[5] H. Liu, W. Deng, H. Jia, S. Zhang, S. Sun, Z. Wang, and B. Chi, “A Multi-Reference PLL: Theory and Implementation,” in IEEE Journal of Solid-State Circuits (JSSC), July 2024（Invited paper）

[6] Q. Wu, W. Deng, Y. Sun, H. Jia, H. Liu, S. Zhang, Z. Wang, and B. Chi, "An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2024.3367351.

[7] F. Zhao, W. Deng, H. Jia, W. Ye, R. Wan, Z. Wang, and B. Chi “A Band-Shifting Millimeter-Wave T/R Front-End using Inductance-mutation Transformer Technique for Multi-band Phased-array Transceivers,” in IEEE Journal of Solid-State Circuits (JSSC) May 2024（Invited paper）

[8] H. Ge, H. Jia, W. Deng, R. Ma, Z. Wang, B. Chi, “A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 7-9, Feb. 2024

[9] Y. Sun, W. Deng, H. Jia, Y. He, Z. Wang and B. Chi, "A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3266426. （Invited paper）

[10] Z. Lin, H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3274178.

[11] Y. Yang, W. Deng, A. Yan, H. Jia, J. Gong, Z. Wang, and B. Chi, “A 10-to-300 MHz Fractional Output Divider with -80 dBc Worst-case Fractional Spurs using Auxiliary PLL based Background 0/1st/2nd-order DTC INL Calibration,” IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2023, pp. 1-3, doi: 10.1109/ISSCC42615.2023.10067785.

[12] Q. Wu, W. Deng, H. Jia, H. Liu, S. Zhang, Z. Wang, B. Chi, “A 11.5-to-14.3 GHz 192.8-dBc/Hz FOM at 1MHz offset Dual-core Enhanced Class-F VCO with Common-mode Noise Self-cancellation and Isolation Technique,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 7-9, Feb. 2023

[13] H. Jia, P. Guan, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS," in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 371-385, Feb. 2023, doi: 10.1109/JSSC.2022.3196181.

[14] W. Deng, Z. Chen, H. Jia, P. Guan, T. Ma, S. Sun, X. Huang, G. Chen, R. Ma, S. Dong, L. Duan, Z. Wang, and B. Chi, “A D-band Joint Radar-Communication CMOS Transceiver,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 411-427, Feb. 2023, doi: 10.1109/JSSC.2022.3185160.

[15] W. Deng, Z. Chen, H. Jia, S. Sun. G. Chen. Z. Wang, and B. Chi, "A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation," IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 4, pp. 1162-1174, April 2022 （Invited paper）

[16] H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A 53.6-to-60.2GHz Many-Core Fundamental Oscillator with Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS," IEEE International Solid- State Circuits Conference (ISSCC), pp. 154-156 Feb. 2022

[17] H. Jia, W. Deng, P. Guan, Z. Wang, and B. Chi,“A 60 GHz 186.5 dBc/Hz FOM Quad-Core Fundamental VCO using Circular-Triple-Coupled-Transformer with No Mode Ambiguity in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021.

[18] W. Deng, Z. Song, R. Ma, J. Lin, J. Ye, S. Kong, S. Hu, H. Jia, and B. Chi, "An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver with Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 8, pp. 2027-2042, Aug. 2020

[19] T. Ma, W. Deng, Z. Chen, J. Wu, W. Zheng, S. Wang, N. Qi, Y. Liu, B. Chi, "A CMOS 76-81 GHz 2TX/3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 2, pp. 233-248, Feb. 2020

[20] H. Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019. （Invited paper）

[21] H.Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019. （Invited to JSSC）

[22] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, and K. Okada, "A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. Invited paper）

[23] H. Liu, Z.Sun, D. Tang, H. Huang, T.Kaneko, Z. Chen, W. Deng, R. Wu and K. Okada, "A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. （Invited paper）

[24] H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, K. Okada, and A. Matsuzawa, "A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC）

[25] H. Liu, Z. Sun, D. Tang, H. Huang, T. Kaneko, W. Deng, R. Wu, K. Okada, and A. Matsuzawa, "An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC）

[26] A. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K.Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -250dB," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, Jul. 2016.（Invited paper）

[27] T. Siriburanon, S.Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W. Deng, M. Miyahara, K. Okada, and A. Matsuzawa, "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No.6 , pp. 1385-1397, Jun. 2016.

[28] T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada, and A. Matsuzawa, "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.

[29] W. Deng, D. Yang, A. Narayanan, K. Nakata, T. Siriburanon, K. Okada, and A. Matsuzawa, "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 252-253, Feb. 2015.

[30] T. Siriburanon, S. Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W.Deng, M. Miyahara, K. Okada, A. Matsuzawa, "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 440-441, Feb. 2015.

[31] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A Fully Synthesizable All-Digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique," IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015. （Invited paper）

[32] W. Deng, S. Hara, A. Musa, K. Okada, and A. Matsuzawa, "A Compact and Low-power Fractionally Injection-Locked Quadrature Frequency Synthesizer using Self-Synchronized Gating Injection Technique for Software-Defined Radios," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.

[33] W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.266-267, Feb. 2014. （Invited to JSSC）

[34] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K.Okada, and A. Matsuzawa, "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014. （Invited paper）

[35] W. Deng, T. Siriburanon, A. Musa, K. Okada, and A. Matsuzawa, "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, Jul. 2013. （Invited paper）

[36] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A 0.022mm2 970µW Dual-loop Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2013. （Invited to JSSC）

[37] W. Deng, K. Okada, and A. Matsuzawa, " Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing", IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp. 429-440, Feb. 2013.