LIU Xiaosen Associate Professor

Phone：+86-10-62771283

Email：liuxiaosen@tsinghua.edu.cn

Address：East Main Building 9-119, School of Integrated Circuits, Tsinghua University, Beijing, China, 100084

Prof. Xiaosen Liu is currently an Associate Professor in the School of Integrated Circuits at Tsinghua University. He received B.S. degree in electrical engineering from Southeast University, China, in 2008, M.Phil. degree supervised by Prof. Kevin Chen (IEEE Fellow) from Hong Kong University of Science and Technology, Hong Kong, in 2011 and Ph.D. degree supervised by Prof. Edgar Sanchez-Sinencio (IEEE Life Fellow) from Texas A&M University, College Station, in 2016. From 2016 to 2022, he worked at the Circuit Research Lab (CRL) of Intel Labs, Oregon, USA as a staff scientist, after which he joined Tsinghua University in 2022. His current research interests include power management, integrated circuits, III-V semiconductor PMIC and electronic design automation. He received many awards including Chinese Government Award for Outstanding Self-Financed Students Abroad, IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award, four-time winner of the Intel Divisional Recognition Awards for the technology achievements, etc. He drove the research in Intel CRL for analog & mixed-signal research, including power management architectures for emerging SoCs, advanced EDA in sub-10-nm CMOS technology, integrated power solution for hardware security. His research promoted many Intel’s product lines including Core™ and Xeon® series processor, PCH chipset, XMM™ 5G Modem, and AES hardware in x86 Arch. He also invented the next-gen Sonicision™ electrosurgical ultrasonic scalpel and proposed the monolithic energy harvesting architecture for IoT. He has been PI/co-PI of several research projects funded by NSF, DARPA, Intel, Medtronic, Texas Instruments, etc. He has published more than 40 articles in top journals and conferences such as ISSCC, IEDM, VLSI, JSSC, TIE and more than 30 U.S. patents. He serves as technical/organizing member for IEEE DAC, ISCAS, etc. and liaison for Semiconductor Research Corporation (SRC).

Group Openings: Our group has openings for 2-4 PhD/Master students every year and regularly recruit postdocs with related background in digital/mixed-signal IC design, power management and EDA. Undergraduate students are also encouraged to participate in our research. For more information, please email liuxiaosen@tsinghua.edu.cn with your CV.

Selected Publications

Patents

■ U.S. Patent No. 010086217B2, “Electrosurgical Ultrasonic Vessel Sealing and Dissecting System,” X. Liu, A. I. Collie-Menchi, J. A. Gilbert, D. A. Friedrichs, K. W. Malan, and E. Sánchez-Sinencio, Covidien.

■ U.S. Patent No. 20180284823A1, “Supply Generator with Programmable Power Supply Rejection Ratio,” X. Liu, T. Na, and H. K. Krishnamurthy, Intel Corporation.

■ U.S. Patent No. US10530254B2, “Peak Delivered Power Circuit for a Voltage Regulator,” K. Ahmed, V. De, N. Desai, S. Kim, K. Krishnamurthy, X. Liu, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

■ U.S. Patent No. 20190006939A1, “Master-Slave Controller Architecture Technical Field,” H. Krishnamurthy, K. Ahmed, V. De, N. Desai, S. Kim, X. Liu, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel Corporation.

■ U.S. Patent No. US10958079B2, “Energy Harvester with Multiple-Input Multiple-Output Switched Capacitor (MIMOSC) Circuitry,” X. Liu, K. Ahmed, V. De, N. Desai, S. Kim, H. Krishnamurthy, T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

■ U.S. Patent No. 20210203228A1, “Non-Linear Clamp Strength Tuning Method and Apparatus,” X. Liu, H. Krishnamurthy, K. Ravichandran, and V. De, Intel.

■ U.S. Patent No. US10845831B2, “Techniques in Hybrid Regulators of High Power Supply Rejection Ratio and Conversion Efficiency,” X. Liu, C. Barrera, H. Krishnamurthy, J. Han, K. Ravichandran, R. Narayana Bhatla, S. Chiu, and V. De, Intel Corporation.

■ U.S. Patent No. 010474174B2, “Programmable Supply Generator,” T. Na, H. K. Krishnamurthy, and X. Liu, Intel.

■ U.S. Patent No. US10897364B2, “Physically Unclonable Function Implemented with Spin Orbit Coupling Based Magnetic Memory,” V. De, K. Ravichandran, H. Krishnamurthy, K. Ahmed, S. Vangal, V. Vaidya, T. Majumder, C. Schaef, S. Kim, X. Liu, and N. Desai, Intel.

■ U.S. Patent No. 20190094931A1, “Energy Harvesting Source and Ambient Condition Tracking in IoT for Adaptive Sensing and Self-modifying Application Code,” K. Ahmed, V. De, N. Desai, S. Kim, H. Krishnamurthy, X. Liu , T. Majumder, K. Ravichandran, C. Schaef, V. Vaidya, and S. Vangal, Intel.

■ U.S. Patent No. US20200350817A1, “Multiple Output Voltage Conversion,” V. De, K. Ravichandran, H. Krishnamurthy, K. Ahmed, S. Vangal, V. Vaidya, T. Majumder, C. Schaef, S. Kim, X. Liu, and N. Desai, Intel.

Journals

■ J. Yang, M. Wang, J. Yu , Y. Wu, J. Cui, T. Li, H. Yang, J. Wang, X. Liu, X. Yang, B. Shen, and J. Wei, “Virtual-Body p-GaN Gate HEMT With Enhanced Ruggedness Against Hot-Electron-Induced Degradation,” IEEE Electron Device Letters (EDL), vol. 45, no. 5, pp. 770-773, May 2024.

■ S. Yin, R. Wang, J. Zhang, X. Liu, and Y. Wang, “Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 3, pp. 705-715, March 2024.

■ J. Yang, J. Wei, Y. Wu, J. Yu, J. Cui, X. Yang, X. Liu, J. Wang, Y. Hao, M. Wang, and B. Shen, “Enhanced robustness against hot-electron-induced degradation in active-passivation p-GaN gate HEMT,” Applied Physics Letters (APL), 4 March 2024;

■ J. Cui, Y. Wu, J. Yang, J. Yu, T. Li, X. Liu, K. Cheng, X. Yang, Y. Hao, J. Wang, B. Shen, M. Wang, and J. Wei, “High-Voltage E-Mode p-GaN Gate HEMT on Sapphire With Gate Termination Extension,” IEEE Transactions on Electron Devices (TED), vol. 71, no. 3, pp. 1592-1597, March 2024.

■ Y. Wu, M. Nuo, J. Yang, W. Lin, X. Liu, X. Yang, J. Wang, Y. Hao, B. Shen, M. Wang, and Jin Wei, “Suppression of Buffer Trapping Effect in GaN-on-Si Active-Passivation p-GaN Gate HEMT via Light/Hole Pumping,” IEEE Transactions on Electron Devices (TED), vol. 71, no. 1, pp. 484-489, Jan. 2024.

■ J. Cui, M. Wang, Y. Wu, J. Yang, H. Yang, J. Yu, T. Li, X. Yang, X. Liu, K. Cheng, J. Wang, B. Shen, and J. Wei, “Demonstration of 1200-V E-Mode GaN-on-Sapphire Power Transistor With Low Dynamic ON-Resistance Based on Active Passivation Technique,” IEEE Electron Device Letters (EDL), vol. 45, no. 2, pp. 220-223, Feb. 2024.

■ X. Liu, S. Yaldiz, P. Mukherjee, S. Burns, H. Krishnamurthy, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and Vivek De, “A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework,” IEEE Solid-State Circuits Letters (SSCL), vol. 6, pp. 101-104, 2023.

■ S. Yin, R. Wang, J. Zhang, X. Liu and Y. Wang, “Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 7, pp. 2080-2093, July 2023.

■ X. Wang, X. Liu and W. -H. Ki, “A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 70, no. 11, pp. 4627-4640, Nov. 2023.

■ D. Das, M. Nath, B. Chatterjee, R. Kumar, X. Liu, H. Krishnamurthy, M. Sastry, S. Mathew, S. Ghosh, and S. Sen, “EM SCA White-box Analysis Based Reduced Leakage Cell Design and Pre-Silicon Evaluation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 11, pp. 4927-4938, Nov. 2022.

■ X. Liu, H. K. Krishnamurthy, T. Na, S. Weng, Z. Ahmed, K. Ravichandran, J. Tschanz, and V. De, “A Universal Modular Hybrid LDO with Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning,” IEEE Journal of Solid-State Circuits (JSSC), invited, 2021.

■ R. Kumar, X. Liu, V. Suresh, H. K. Krishnamurthy, S. Satpathy, M. Anders, K. Himanshu, K. Ravichandran, V. De, and S. K. Mathew, “A Time/Frequency-domain Side-channel Attach Resistant AES-128 and RSA-4K Crypto-Processor in 14nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 56, no. 4, pp. 1141-1151, Apr. 2021.

■ X. Liu, H. K. Krishnamurthy, C. Barrera, J. Han, R. M. Narayana Bhatla, S. Chiu, Z. K. Ahmed, N. Desai, K. Ravichandran, J. W. Tschanz, V. De, “A Dual-Rail Hybrid Analog/Digital Low Dropout Regulator with Dynamic Current Steering for a Tunable High PSRR and High Efficiency,” IEEE Solid-State Circuits Letters, vol. 3, pp. 526-529, 2020.

■ Z. Ahmed, H. Krishnamurthy, C. Augustine, X. Liu, W. Sheldon, K. Ravichandran, J. Tschanz, and V. De, “A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 55, no. 4, pp. 977-987, Apr. 2020.

■ C. Schaef, D. Nachiket, K. Harish, X. Liu, Z. Ahmed, K. Suhwan, W. Sheldon, H. Do, W. Lambert, K. Ravichandran, K. Radhakrishnan, J. Tschanz, and V. De, “A Light-Load Efficient Fully Integrated Voltage Regulator in 14 nm CMOS with 2.5 nH Package-Embedded Air-Core Inductors,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 54, no. 12, pp. 3316-3325, Dec. 2019.

■ H. Krishnamurthy, V. Vaidya, P. Kumar, R. Jain, S. Weng, S. Kim, G. Matthew, N. Desai, X. Liu, K. Ravichandran, J. Tschanz, and V. De, “A Digitally Controlled Fully Integrated Voltage Regulator with On-Die Solenoid Inductor with Planar Magnetic Core in 14nm Tri-Gate CMOS,” IEEE Journal of Solid-State Circuits (JSSC), invited, vol. 53, no. 1, pp. 8-19, Jan. 2018.

■ X. Liu, A. Colli-Menchi, and E. Sanchez-Sinencio, “Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator,” IEEE Transaction on Biomedical Circuits and Systems (BioCAS), invited, vol. 11, no. 6, pp. 1226-1235, Dec. 2017.

■ X. Liu, L. Huang, K. Ravichandran, and E. Sanchez-Sinencio, “A Highly Efficient Reconfigurable Charge Pump Energy Harvester with Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 5, pp. 1302-1312, May 2016.

■ X. Liu and E. Sanchez-Sinencio, “An 86% Efficiency 12 μW Self-sustaining PV Energy Harvesting System with Hysteresis Regulation and Time-domain MPPT for IOT Smart Nodes,” IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 6, pp. 1424-1437, Mar. 2015.

■ X. Liu, A. Colli-Menchi, J. Gilbert, D. Friedrichs, K. Malang, and E. Sanchez-Sinencio, “An Automatic Resonance Tracking Scheme With Maximum Power Transfer for Piezoelectric Transducers,” IEEE Transactions on Industrial Electronics (TIE), vol.62, no.11, pp.7136-7145, Nov. 2015.

■ A.M.H. Kwan, G. Yue, X. Liu, K.J. Chen, “A Highly Linear Integrated Temperature Sensor on a GaN Smart Power IC Platform,” IEEE Transactions on Electron Devices (TED), vol. 61, no. 8, pp. 2970-2976, Aug. 2014.

■ X. Liu, K. J. Chen, “GaN Single-Polarity Power Supply Bootstrapped Comparator for High Temperature Electronics,” IEEE Electron Device Letters (EDL), vol. 32, No. 1, pp. 27-29, Jan. 2011.

Conference Proceedings

■ C. Hu, X. Huang, X. Liu, S. Du, X. Liu, and J. Jiang, “A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver Applications,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 508-510.

■ S. Kim, H. K Krishnamurthy, Z. Ahmed, N. Desai, S. Weng, A. Augustine, H. T. Do, J. Yu, P. D. Bach, X. Liu, K. Radhakrishnan, K. Ravichandran, J. W. Tschanz, and V. De, “A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 270-272.

■ Z. Wang, J. Zhou, X. Liu and Y. Wang, “An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits,” 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Incheon, Korea, Republic of, 2024, pp. 417-422.

■ J. Cui, J. Wei, M. Wang, Y. Wu, J. Yang, T. Li, J. Yu, H. Yang, X. Yang, J. Wang, X. Liu, D. Ueda, B. Shen, “6500-V E-mode Active-Passivation p-GaN Gate HEMT with Ultralow Dynamic RON,” International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4.

■ X. Liu, S. Yaldiz, P. Mukherjee, S. Burns, H. Krishnamurthy, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and V. De, “A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, 2022, pp. 2-4.

■ H. Wang, R. Liu, R. Dorrance, D. Dasalukunte, X. Liu, D. Lake, B. Carlton, and M. Wu, “A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference,” IEEE Symposium on VLSI Technology and Circuits (VLSI), Honolulu, HI, USA, 2022, pp. 36-37.

■ X. Liu, H. Krishnamurthy, R. Liu, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, and V. De, “A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 478-479, Feb. 2022.

■ Z. Ahmed, N. Desai, H. Krishnamurthy, S. Weng, X. Liu, K. Ravichandran, J. Tschanz, and V. De, “A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2021.

■ n N. Desai, H. Krishnamurthy, Z. Ahmed, S. Weng, S. Kim, X. Liu, H. Do, K. Radhakrishnan, K. Ravichandran, J. Tschanz, V. De, “Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 262-263, Feb. 2021.

■ X. Liu, H. Krishnamurthy, C. Barrera, J. Han, R. Narayana Bhatla, S. Chiu, Z. Ahmed, K. Ravichandran, J. Tschanz, and V. De, “A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR & High Efficiency,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

■ R. Kumar, X. Liu, V. Suresh, H. Krishnamurthy, M. Anders, H. Kaul, K. Ravichandran, V. De, and S. Mathew, “A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-linear Digital LDO Cascaded with Arithmetic Countermeasures,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

■ Z. Ahmed, H. Krishnamurthy, S. Weng, X. Liu, C. Schaef, N. Desai, K. Ravichandran, J. Tschanz, and V. De, “An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering,” IEEE Symposia on VLSI Technology & Circuits (VLSI), Jun. 2020.

■ Z. Ahmed, H. Krishnamurthy, C. Augustine, X. Liu, S. Weng, K. Ravichandran, J. Tschanz, and V. De, “A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response,” IEEE Symposia on VLSI Technology & Circuits (VLSI), pp. 124-125, Jun. 2019.

■ X. Liu, H. K Krishnamurthy, T. Na, S. Weng, K. Z Ahmed, K. Ravichandran, J. Tschanz, V. De, “A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 234-235, Feb. 2019.

■ S. Kim, V. Vaidya, C. Schaef, A. Lines, H. Krishnamurthy, S. Weng, X. Liu, D. Kurian, T. Karnik,K. Ravichandran, J. Tschanz, and V. De, “A Single-Stage, Single-Inductor, 6 Input 9 Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120mW Battery Powered IoT Edge Nodes,” IEEE Symposia on VLSI Technology and Circuits (VLSI), pp. 195-196, Jun. 2018.

■ X. Liu, A. Colli-Menchi, and E. Sanchez-Sinencio, “A Reduced-Order Sliding-Mode Controller with an Auxiliary PLL Frequency Discriminator for Ultrasonic Electric Scalpels,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 358-359, Feb. 2017.

■ X. Liu and E. Sanchez-Sinencio, “A Single-cycle MPPT Charge Pump Energy Harvester using a Thyristor-based VCO without Storage Capacitor,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 364-365, Feb. 2016.

■ X. Liu and E. Sanchez-Sinencio, “A 0.45-to-3V Reconfigurable Charge-Pump Energy Harvester with Two-Dimensional MPPT for Internet of Things,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 370-371, Feb. 2015.

■ A. M. H. Kwan, X. Liu, and K. J. Chen, “Integrated gate-protected HEMTs and mixed-signal functional blocks for GaN smart power ICs,” IEEE International Electron Devices Meeting (IEDM), pp.7.3.1-4, Dec. 2012.